1. Field of the Invention
The present invention relates to a video decoder with a down conversion function, and a method for decoding a video signal.
2. Background of the Related Art
In general, an MPEG-2 video decoding chip is provided with a TP (Transport Packet)-decoder, a video decoder, a video display processor, an external memory, and a host interface, and the like. The external memory may be a DRAM (Dynamic Random Access Memory) for receiving, and storing a bitstream, and frame buffers for motion compensation, and the like. MPEG-2 standard requires a bit buffer size of 16 Mbits for supporting an MP@HL mode, at a maximum allowable bit rate of 80 Mbits/s. An existing 16 Mbits DRAM basis MPEG-2 decoder requires an external memory of approx. 96xcx9c128 Mbits size. Therefore, a price competitiveness is required in view of manufacturers and consumers. For having the price competitiveness, it is required that a good picture quality is maintained while expensive memory sizes are reduced. However, it is foreseen that an increase of additional external memories is inevitable in the future in light of a trend that various OSD (On Screen Display) and a variety of services are provided.
Recently, in a case of a video compression and decoding system such as MPEG-2, a variety of video signals are multi-decoded and displayed, for providing a variety of services, when it is required that the variety of video signal are decoded by using a limited capacity of the memory. At the end, taking the memory size limitation, price, and a bandwidth of a data bus into account, the video decoding chip is required to be provided with an effective device for reducing a memory capacity that can minimize a loss of a high quality picture signal loss.
In memory reduction algorithms loaded on existing video decoding chips, there are the ADPCM (Adaptive Differential Pulse Coded Modulation) type with a 50% reduction ratio, and the type with 75% reduction ratio that eliminates spatial duplicity by using VQ (Vector Quantization).
The ADPCM is suggested by Pau and Sano in EP 0778709A1 titled xe2x80x9cMPEG-2 decoding with a reduced RAM requisite by ADPCM recompression before storing MPEG decompressed dataxe2x80x9d. The VQ is suggested by Bruni et al. in IEEE Trans., On Customer Electronics, pp. 537-544, 1988, titled xe2x80x9cA novel adaptive vector quantization method for memory reduction in MPEG-2 HDTV decodersxe2x80x9d.
Compression methods by filtering in a DCT (Discrete Cosine Transformation) frequency domain, or down sampling are suggested by S.-B. Ng (xe2x80x9cLower resolution HDTV receiversxe2x80x9d, U.S. Pat. No. 5,362,854, Nov. 16, 1993), S.-J. Choi et al. (xe2x80x9cFrame memory reduction for MPEG-2/DTV video codingxe2x80x9d, Int. workshop on HDTV ""98), and R. Mokry and D. Anastassiou (xe2x80x9cMinimul error drift in Frequency scalability for motion-compensated DCT codingxe2x80x9d, IEEE Trans. On Circuits and Systems for Video Tech., Vol. 4, August 1994).
Because a compressed code is stored in the memory, the ADPCM method is difficult to display a video by using a video display right away, to require a device for decoding the compressed code, additionally. Since the ADPCM method shows very great picture quality loss in a case of 75% reduction, the ADPCM method is not suitable for the video decoding chip.
Different from this, a plurality of HDTV class videos or SD class videos received at one chip video decoder can be displayed on one screen simultaneously by using a down conversion algorithm. This method can maintain a good picture quality to some extent despite of substantial reduction of the memory capacity, and applicable to inexpensive decoders for low resolution displays. Therefore, a down conversion algorithm that allows to employ a small capacity memory while a good picture quality can be maintained, and a hardware design for the down conversion algorithm, are required.
A general MPEG encoder encodes either a progressive sequence or an interlaced sequence. An interlaced sequence picture is encoded in field or frame units. The field picture has odd scanning lines and even scanning lines, and all encoder and decoder are operative in field. Therefore, data blocks each DCT Transformed in a 8xc3x978 unit only has odd fields or even fields, which are called as field DCT coded blocks.
Different from this, a frame picture has odd scanning lines and even scanning lines, resulting in macro blocks of the frame picture to have odd fields and even fields. However, macro blocks of the frame picture can be coded in two methods. According to the first method, each of the four 8xc3x978 discrete cosine transformed blocks is a DCT coded block in frame units each having odd scanning lines and even scanning lines. On the other hand, according to the second method, two macro blocks from the four macro blocks are blocks DCT coded in field units only having odd scanning lines of the macro blocks, and the rest of two macro blocks are blocks DCT coded in field units only having even scanning lines.
All the macro block in the field picture are DCT coded in field units, and motion compensation of which are predicted from a reference field in making motion compensation. On the other hand, macro blocks in the frame picture are DCT coded in frame units or in field units. Each of the macro blocks in the frame picture is motion compensation predicted in frame units or field units. On the other hand, in a case of the progressive sequence, all pictures are DCT coded, and motion compensation predicted in frame units.
Currently, in this state spread of HD displays are not enough, there are many cases when an HD class picture quality video sequence is displayed in a lower resolution through TV receivers of present NTSC (National Television System Committee) standards. Therefore, it is required that users can watch an HDTV broadcasting signal through the NTSC TV receivers without buying expensive HDTV (High Definition Television), immediately. As explained, a device for converting the HDTV broadcasting signal suitable to the NTSC TV receiver is called as a down converting decoder. At the end, by employing the down converting decoder, a TV receiver having a price significantly lower than a TV receiver having a perfect HD class resolution can be obtained.
One of these types is disclosed in U.S. Pat. No. 5,262,854. This patent includes a down sampler for removing 48 high frequency DCT coefficients in an 8xc3x978 block. According to this patent, a result of IDCT for the rest low frequency 4xc3x974 blocks is stored in a memory. Therefore, for making an accurate motion compensation, when it is intended to reduce an error of motion compensation prediction by using perfect resolution motion vectors, a frame of reduced resolution is used as reference. At the end, in order to provide a picture of a perfect resolution from a picture of a reduced resolution, an up-sampling is employed.
A few effective methods are suggested for reducing the error of motion compensation prediction by up sampling a picture down sampled by using 4xc3x974 IDCT, by R. Monky and D. Anastsssiou (xe2x80x9cMinimul error drift in frequency scalability for motion-compensated DCT codingxe2x80x9d, IEEE Trans. On circuits and systems for video Tech., Vol. 4, No. 4, August 1994), and Johnson and Princen (xe2x80x9cDrift minimization in frequency scaleable coders using block based filteringxe2x80x9d, IEEE workshop on visual signal processing and communication, September 1993. These methods employ two dimensional filters each having 5 taps or 8 taps depending on a typically predicted motion vector of a macro block, when positions of 8 tap filter values are changed depending on the motion vector, to require to increase 4 pels into 8 pels by one 8 tap filter.
However, while the foregoing methods are suitable to a progressive sequence having DCT coded blocks in frame units, matters on a video of blocks DCT coded in frame units and DCT coded in field units mixed therein are not taken into account. Moreover, the foregoing methods have a frame type memory structure, a down converting of blocks DCT coded in field units is carried out after the blocks DCT coded in field units is converted into blocks DCT coded in frame units, that results in unfavorable influence of prediction error accumulation in making motion compensation in an area having a great motion. Furthermore, the only employment of low frequency parts (in general, called as 4xc3x974 cuts) among 8xc3x978 DCT coefficients in the motion compensation causes to lost signals of high frequency band, that causes to occur block artifacts.
Eventually, an interlaced sequence processed at an MPEG-2 video decoder has a problem of data loss occurred in the down conversion.
Accordingly, the present invention is directed to a video decoder with a down conversion function, and a method for decoding a video signal that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a video decoder with a down conversion function, and a method for decoding a video signal which permits an SD class display of a small memory capacity to display an HD class signal.
Another object of the present invention is to provide a video decoder with a down conversion function, and a method for decoding a video signal which permits to reduce different video signals in 1/2, or 3/4 reduction ratio, and store in an external memory at a time, or display on one screen at a time, regardless of a progressive scanning type picture or interlaced scanning type picture.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, and according to a first characteristic of the present invention, frame DCT coded blocks and field DCT coded block received at the video decoder are always down converted into a picture of a field basis vertical pel structure.
According to a second characteristic of the present invention, a macro block adder module adds a motion compensated macro block from a motion compensation buffer and an IDCT macro block from a DCT buffer according to a picture structure and a DCT type. In a 75% reduction mode, a device is included for arranging positions of pels of a block predicted as a field structure to suit to an IDCT type.
According to a third characteristic of the present invention, a down sampler module has modes for horizontal 1/2 reduction in 8xc3x978 block units, and for vertical and horizontal 3/4 reductions.
According to a four characteristic of the present invention, a down sampler module divides a frame DCT coded block into field signals and extracts frequency components in a 8xc3x978 block in a 3/4 reduction mode. In this instance, different down sampling filters are used in a vertical down sampling depending on a color component, because a number of fields for chrominance components are smaller than a number of fields for luminance components.
According to a fifth characteristic of the present invention, in a down sampling, down sampled pels are obtained by a down sampling matrix conversion. That is, C4xc3x978=C4Txc2x7T8, where       C4    =                  [                                                            T                4                                                                        φ                                      ]                    2              ,
and T4 denotes a 4xc3x974 DCT basis matrix, except that C2xc3x974=C2Txc2x7T4 filter is used in vertical down sampling of a chrominance component.
According to a sixth characteristic of the present invention, in motion compensation, a field fit to a motion vector is selected, and reads a reduced field reference signal on a memory. Then, horizontal and vertical direction up sampling are carried out for each fields.
According to a seventh characteristic of the present invention, in field prediction compensation, a reference address is provided to a memory by using a motion vector to read a reference block. Then, horizontal and vertical up sampling is carried out for each filed, a 1/2 pel prediction is made for the up sampled blocks, to provide motion compensated blocks. Finally, the motion compensated blocks are forwarded to a macro block adder in field units.
According to an eighth characteristic of the present invention, in frame prediction compensation, a reference address is provided to a memory by using a motion vector, to read field unit reference blocks. Then, horizontal and vertical up sampling is carried out for each field, and a frame unit reference block is formed of up sampled blocks of each field. Then, a motion compensated block is formed by making 1/2 pel prediction. Finally, motion compensated frame unit blocks are forwarded to a macro block adder according to IDCT macro block type.
According to a ninth characteristic of the present invention, an up sampler module has a 1/2 reduction mode in which a horizontal up sampling in 8xc3x974 block units is made, and a 3/4 reduction mode in which vertical and horizontal up sampling in 4xc3x974 block units are made.
According to a tenth characteristic of the present invention, a motion compensator uses 2xc2x7C4xc3x978T, and 2xc2x7C2xc3x974T filters in up sampling in filtering.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.